The disclosures herein relate generally to processors, and more specifically, to processors that employ instruction issue queue dependency management for load and store instructions.
Modern information handling systems (IHSs) may include load and store instructions within an instruction issue queue that a processor fetches and decodes from an instruction data stream. A processor load/store unit (LSU) executes the load and store instructions as they issue from the issue queue. Issue queue and LSUs maintain a finite amount of storage space for instruction data. Processors manage the storage limitations for load and store instructions by limiting the allocation of LSU entries. Processors monitor LSU instruction execution status to determine when a new load or store instruction may issue from the issue queue into the LSU.
Because out-of-order instruction handling is common in modern IHSs, processors typically track the dependencies between instructions pending issue in the instruction issue queue. A particular instruction may not issue until dependencies for that particular instruction are met. Those dependencies may include data dependencies, address dependencies, and other dependencies. When each of the particular instruction dependencies clear, that particular instruction may issue to an execution unit, such as the LSU within the processor, for further processing.